The present invention relates to a semiconductor device and a method for fabricating the same and, more particularly, to a highly-integrated and miniaturized LSI device and a method for fabricating the same.
There have been growing expectations on Cu interconnects having low electric resistance and high resistance to electromigration (EM) as a material for interconnects in a highly-integrated and miniaturized LSI device.
However, the microfabrication of Cu interconnects is extremely difficult. As one of effective methods for implementing microfabricated Cu interconnects, a damascene method which buries a Cu film in an underlying film to which via-hole/interconnect-trench forming processes have been performed can be listed. As means for burying the Cu film, an electrolytic plating method can be listed.
A description will be given herein below to a method for fabricating a semiconductor device comprising Cu interconnects formed by using a damascene method with reference to FIGS. 4A to 4C and FIGS. 5A and 5B (see, e.g., Non-Patent Document 1: IEEE, IITC 2003, pp. 97-99, FIG. 7). FIGS. 4A to 4C and FIGS. 5A and 5B are cross-sectional views illustrating the principal process steps of the method for fabricating the semiconductor device according to a conventional embodiment.
First, as shown in FIG. 4A, lower interconnects 301 composed of a Cu film 301b are formed in an interlayer insulating film 300 formed on a substrate (not shown) each with a barrier metal 301a interposed therebetween. Then, a low-dielectric-constant film 302 is formed on the interlayer insulating film 300. Subsequently, dry etching is selectively performed with respect to the low-dielectric-constant film 302, thereby forming via holes 303 for exposing the upper surfaces of the lower interconnects 301 in the low-dielectric-constant film 302 and forming interconnect trenches 304 connecting to the respective via holes 303 also in the low-dielectric-constant film 302. Next, as shown in FIG. 4B, a barrier metal 305 made of, e.g., TaN, TiN, or WN is formed over the sidewalls and bottom portions of the via holes 303, the sidewalls and bottom portions of the interconnect trenches 304, and the upper surface of the low-dielectric-constant film 302. Then, as shown in FIG. 4C, a seed layer 306 for electrolytic plating made of Cu is formed on the barrier metal film 305.
Next, as shown in FIG. 5A, Cu is buried in each of the via holes 303 and the interconnect trenches 304 by using an electrolytic plating method so that a plate layer 307 made of Cu is formed. At this time, since Cu composing the seed layer 306 is diffused into the plate layer 307, the boundary line between the seed layer 306 and the plate layer 307 cannot be substantially recognized so that it is not shown. Then, as shown in FIG. 5B, the respective portions of the barrier metal 305 and the plate layer 307 which are located outside the interconnect trenches 304 are removed by CMP till the surface of the low-dielectric-constant film 302 is exposed, whereby surface planarization is performed.
In this manner, an interconnect plug composed of buried Cu is formed in each of the via holes 303 with the barrier metal 305 interposed therebetween, while an upper interconnect 308 composed of buried Cu is formed in each of the interconnect trenches 304 also with the barrier metal 305 interposed therebetween.
In the recent device development, the use of a low-dielectric-constant film having voids therein has been examined with the view to further reducing the low dielectric constant of a low-dielectric-constant film.
A description will be given herein below to a method for forming a low-dielectric-constant film having voids therein.
A solution containing organic particles having sizes substantially equal to the objective sizes (diameters of, e.g., about 1 nm) of the voids is applied onto an interlayer insulating film having lower interconnects. Subsequently, by removing the organic particles contained in the applied solution at a low temperature (specifically, at a temperature of 100° C. to 200° C.), a coating layer for forming the low-dielectric-constant film can be formed. Thus, the coating layer having the voids formed through the removal of the organic particles has been formed by selecting organic particles having desired sizes as the organic particles contained in the applied solution. Since the sizes of the voids derive from the sizes of the organic particles, each of the organic particles is termed a porogen or template.
By applying a solution containing, e.g., a material (e.g., NCS or the like) having internal voids of minute sizes (diameters of, e.g., about 1 nm) on an interlayer insulating film having lower interconnects, a coating layer for a low-dielectric-constant film having voids of desired sizes can be formed (see, e.g., Non-Patent Document 2: IEEE, IITC 2004, pp. 175-177, FIG. 1). Thus, the coating layer having the voids has been formed by selecting a material having internal voids of desired sizes as the material contained in the applied solution.
In each of the cases described above, the low-dielectric-constant film having the internal voids of desired sizes (diameters of, e.g., about 1 nm to about 2 nm) can be formed by forming the coating layer having the internal voids of desired sizes and then annealing the coating layer by a thermal process at a temperature of 400° C.
However, the method for fabricating the semiconductor device according to the conventional embodiment has had the following problems. A description will be given to the problems encountered by the method for fabricating the semiconductor device according to the conventional embodiment with reference to FIGS. 6A and 6B. FIGS. 6A and 6B are cross-sectional views illustrating the principal process steps of the method for fabricating the semiconductor device according to the conventional embodiment.
When the low-dielectric-constant film (hereinafter referred to as a porous low-dielectric-constant film) 302 having voids therein is used in the method for fabricating the semiconductor device according to the conventional embodiment, the voids (not shown) having diameters of about 1 nm to about 2 nm are exposed at the regions of the porous low-dielectric-constant film 302 to which dry etching has been performed in the step of forming the via holes 303 and the interconnect trenches 304 (see FIG. 4A mentioned above), i.e., at the sidewalls of the via holes 303 and at the bottom portions and sidewalls of the interconnect trenches 304.
Consequently, the barrier metal 305 is formed directly over the sidewalls of the via holes 303 and the bottom portions and sidewalls of the interconnect trenches 304 having respective surfaces at which the voids are exposed in the step of forming the barrier metal 305 (see FIG. 4B mentioned above). As a result, a material (such as, e.g., TaN, TiN, or WN) composing the barrier metal 305 is diffused into the porous low-dielectric-constant film 302 via the voids so that diffusion regions 400 are formed to cause the problem of the degraded barrier property of the barrier metal 305, as shown in FIG. 6A.
Accordingly, the barrier metal 305 cannot sufficiently perform the function as the barrier film so that the material Cu composing the plate layer 307 passes through the barrier metal 305 and is further diffused into the porous low-dielectric-constant film 302 via the voids to form Cu diffusion regions 401, as shown in FIG. 6B. During the operation of the semiconductor device also, the material Cu composing the plate layer 307 is further diffused into the porous low-dielectric-constant film 302.
Thus, in the method for fabricating the semiconductor device according to the conventional embodiment, the barrier property of the barrier metal 305 deteriorates so that the material Cu composing the plate layer 307 is diffused into the porous low-dielectric-constant film 302 during the fabrication and operation of the semiconductor device. As a result, the Cu diffusion regions 401 are formed so that a leakage current flows between the individual upper interconnects 308 through the path R, as shown in FIG. 6B. This causes the problem of the faulty operation of the semiconductor device and also causes the problem of a significant reduction in the production yield of the semiconductor device.
As a technology for solving these problems, a method has been proposed which causes a plasma by-product generated during dry etching to be deposited on the surface of the porous low-dielectric-constant film in the step of forming the via holes and the interconnect trenches and thereby clogs the voids exposed at the surfaces of the porous low-dielectric-constant film (see, e.g., Non-Patent Document 3: IEEE, IITC 2004, pp. 39-41).
In accordance with the method mentioned above, however, it is difficult to cause a plasma by-product to be deposited with high reproducibility on the surfaces (especially on the portions of the porous low-dielectric-constant film at which the voids are exposed) of the porous low-dielectric-constant film. Accordingly, it has been difficult to reliably clog the voids exposed at the surfaces of the porous low-dielectric-constant film.